combinational logic design
基本解釋
- [電子、通信與自動控制技術(shù)]組合邏輯設(shè)計
英漢例句
- It can also generate a MOS element connection table for Mos circuits The logic design automation of combinational MOS circuits is preliminarily realized.
由開關(guān)級代數(shù)表達(dá)式導(dǎo)出其等價的MOS元件聯(lián)接關(guān)系表的算法; 從而初步實(shí)現(xiàn)了組合MOS電路的邏輯設(shè)計自動化。 - To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.
根據(jù)組合邏輯電路的設(shè)計方法,突出用卡諾圖化簡邏輯表達(dá)式在并聯(lián)比較型A/D轉(zhuǎn)換器編碼電路設(shè)計中的應(yīng)用。 - In this paper the writer tries to integrate the design of asynchronos counters of arbitrary carry system with the design of combinational logic circuits in concept and method.
本文試圖把時序邏輯電路和組合邏輯電路的設(shè)計,在概念上和方法上統(tǒng)一起來。
雙語例句
詞組短語
- Combinational Logic Circuit Design 組合邏輯電路設(shè)計
- Combinational Logic Design Principles 嘅
- Combinational Logic Design Practices 嘅
- design combinational logic circuits 組合邏輯電路設(shè)計
短語
專業(yè)釋義
- 組合邏輯設(shè)計